\doxysection{CORDIC\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_c_o_r_d_i_c___type_def}{}\label{struct_c_o_r_d_i_c___type_def}\index{CORDIC\_TypeDef@{CORDIC\_TypeDef}}


COordincate Rotation DIgital Computer.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_o_r_d_i_c___type_def_a60112828255218fbee25d903849dee11}{CSR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_o_r_d_i_c___type_def_a6aee85de788bab17b8235aa67aebdec6}{WDATA}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_o_r_d_i_c___type_def_a8c7994072a36a96856762f4d3394892e}{RDATA}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
COordincate Rotation DIgital Computer. 

\label{doc-variable-members}
\Hypertarget{struct_c_o_r_d_i_c___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_c_o_r_d_i_c___type_def_a60112828255218fbee25d903849dee11}\index{CORDIC\_TypeDef@{CORDIC\_TypeDef}!CSR@{CSR}}
\index{CSR@{CSR}!CORDIC\_TypeDef@{CORDIC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CSR}{CSR}}
{\footnotesize\ttfamily \label{struct_c_o_r_d_i_c___type_def_a60112828255218fbee25d903849dee11} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CORDIC\+\_\+\+Type\+Def\+::\+CSR}

CORDIC control and status register, Address offset\+: 0x00 \Hypertarget{struct_c_o_r_d_i_c___type_def_a8c7994072a36a96856762f4d3394892e}\index{CORDIC\_TypeDef@{CORDIC\_TypeDef}!RDATA@{RDATA}}
\index{RDATA@{RDATA}!CORDIC\_TypeDef@{CORDIC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RDATA}{RDATA}}
{\footnotesize\ttfamily \label{struct_c_o_r_d_i_c___type_def_a8c7994072a36a96856762f4d3394892e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CORDIC\+\_\+\+Type\+Def\+::\+RDATA}

CORDIC result register, Address offset\+: 0x08 \Hypertarget{struct_c_o_r_d_i_c___type_def_a6aee85de788bab17b8235aa67aebdec6}\index{CORDIC\_TypeDef@{CORDIC\_TypeDef}!WDATA@{WDATA}}
\index{WDATA@{WDATA}!CORDIC\_TypeDef@{CORDIC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WDATA}{WDATA}}
{\footnotesize\ttfamily \label{struct_c_o_r_d_i_c___type_def_a6aee85de788bab17b8235aa67aebdec6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CORDIC\+\_\+\+Type\+Def\+::\+WDATA}

CORDIC argument register, Address offset\+: 0x04 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
